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Designing with Chiplets to Build The Dream Chip

In this episode, we talk about chiplets, 3D stacking, heterogenous integration, and multi-die systems design. Stanford University’s Subhasish Mitra talks about his keynote at the HiPEAC conference, where he talked about using computation immersed in memory to break down the memory wall and the scaling wall and build a dream chip delivering 1000x energy efficiency. And then, we talk to Cadence, Synopsys, and Eliyan about some of the opportunities and challenges for chiplet design.

Hello, welcome to this edition of Embedded Edge with Nitin. In this episode, we talk to various people on the subject of chiplets, 3D stacking, heterogenous integration, and multi-die systems design – quite timely since we just saw the first Chiplet Summit take place in California in January. As the summit’s general chair, Chuck Sobey, said, “Chiplets can do much to increase chip scalability, modularity, and flexibility.  But the idea only works if product developers can integrate them quickly and cheaply.  Effective integration platforms require many tools.  Vendors in all areas must provide a platform and support an ecosystem and open-source efforts to fill the interface and software gaps.”

So on that topic, I managed to get a great chat with one of the most prominent people in this area, Subhasish Mitra, professor of electrical engineering and of computer science at Stanford University, and someone who’s been working on next-generation computing immersed in-memory architectures. Having spent time in the industry and now for over 15 years at Stanford, he really is considered a thought leader in this area. He and his students have published over 10 award-winning papers across 5 topic areas on technology, circuits, EDA, test, and verification at major conferences, including the Design Automation Conference, International Solid-State Circuits Conference, International Test Conference, and others.

We chatted at the HiPEAC conference in Toulouse, France, one of the key European conferences dedicated to the high-performance computing community, where Mitra gave the opening keynote talk.

In this podcast, I also get the perspectives of others involved in chiplet design and connectivity. In the second interview, you’ll hear from Vinay Patwardhan, product management group director in the digital implementation and 3D IC products at Cadence; then we hear from Patrick Shoheili, co-founder & head of business and corporate development at Eliyan; and the final discussion is with Shekhar Kapoor, a senior director at Synopsys focused on multi-die systems.

By EETimes