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Different types of SiP (system in package) solutions are facing diverse challenges, and can be materialized only through close cooperation among related semiconductor supply chain players, according to CP Hung, vice president of R&D at ASE Technology.
Hung said at an online Heterogeneous Integration Global Summit being held by SEMI that integration of silicon wafers, third-generation compound components such as GaN, and multiple passive components will boost the complexity of SiP solutions.
He said that if a SoC is to be scaled down by 15-30% in size, it has to rely on new wafer and components miniaturization technologies, new materials and more-advanced packaging processes.
Hung stressed that heterogeneous integration actually covers every aspect of the semiconductor supply chain, and ASE can handle the entire SiP processes, ranging from design, components integration to packaging and testing. Its current solutions comprise leadframe, BGA (ball grid array), FC (flip chip), fan-out, 2.5D and even 3D IC packaging processes.
Hung said foundry houses can cut into the SoC field with chip-on-wafer (CoW) and SoIC technology, indicating the multiplicity of heterogeneous integration that can be achieved from the chip side or the package side combining system solution technologies.
On the same occasion, SEMI Taiwan president Terry Tsao noted that demand for IC packaging and testing equipment will continue to grow along with the increasing complexity of IC designs and mounting demand for 5G and HPC chips. SEMI estimates that global market for semiconductor testing equipment will grow 26% on year to US$7.6 billion in 2021 and surge further to US$8 billion in 2022, while global sales of IC packaging equipment will jump 50% to US$6 billion in 2021.