Ever since Ventana Micro Systems came out of stealth last year, the company has been busily developing relationships with partners and potential customers to create traction for its RISC-V–based chiplets, which it believes will address the high-performance computing demands in data centers and at the edge.

Now, the company has raised $55 million in new funding to productize its chiplets based on open standard die–to–die (D2D) interfaces.

The excitement and enthusiasm Balaji Baktha, founder and CEO of Ventana, has for chiplets solving the computing challenges created by the demands in data center, automotive, and 5G is very apparent. EE Times heard it firsthand, in an exclusive interview with the CEO at the recent 59^th Design Automation Conference (DAC) in San Francisco.

At DAC, he said he believed this was being reflected in the market, too—especially around open source and RISC–V, the latter being something Intel Foundry Services (IFS) has been pushing a lot (see “DAC 2022: Digital twins and the door to the metaverse”).

“DAC was all about how you enable the next wave of compute density,” he said. “It was about chiplets, about open compute and open hardware, and RISC–V. With UCIe (Universal Chiplet Interconnect Express) now beginning to take shape, Ventana is working closely and strategically with Intel to bring UCIe–based chiplets to market. The latest funding will allow us to get there, and we expect tape out of our first UCIe chiplet products in the second half of 2023.”

The UCIe is an open specification that aims to define the interconnect between chiplets within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level (see “Chiplets Get a Formal Standard with UCIe 1.0”). The founding members of the UCIe consortium include AMD, Arm, Advanced Semiconductor Engineering, Inc. (ASE), Google Cloud, Intel Corporation, Meta, Microsoft, Qualcomm, Samsung, and TSMC. Alibaba and Nvidia joined the consortium this month.

“We will be one of the first in the market to productize chiplets for UCIe, and we are working closely with Intel to make these available,” Baktha said.

Supporting this vision, Bob Brennan, VP of customer solutions engineering at IFS, said, “RISC–V offers a level of scalability and customization that is unique in the industry. We are seeing strong demand from our customers to support high–performance RISC–V solutions.”

On the chiplet progress, he added, “Ventana has the most complete and well developed open chiplet–based platform, which is well aligned to Intel’s vision. Ventana’s chiplets enable IFS to deliver modular solutions that increase performance, reduce power, reduce development cost and accelerate time to market.”

By EETimes